好用的Verilog串口UART程序

文章摘要：reg rx_d1 ;reg rx_d2 ;reg rx_busy ;// UART RX Logicalways @ (posedge rxclk or posedge reset)if (reset) beginrx_reg <= 0; rx_data <= 0;rx_sample_cnt <= 0;rx_cnt <= 0;rx_frame_err <= 0;rx_over_run <= 0;rx_empty

好用的Verilog串口UART程序,标签：eda技术,eda技术实用教程,http://www.88dzw.com
reg          rx_d1          ;
reg          rx_d2          ;
reg          rx_busy        ;

// UART RX Logic
always @ (posedge rxclk or posedge reset)
if (reset) begin
rx_reg        <= 0;
rx_data       <= 0;
rx_sample_cnt <= 0;
rx_cnt        <= 0;
rx_frame_err <= 0;
rx_over_run   <= 0;
rx_empty      <= 1;
rx_d1         <= 1;
rx_d2         <= 1;
rx_busy       <= 0;
end else begin
// Synchronize the asynch signal
rx_d1 <= rx_in;
rx_d2 <= rx_d1;
// Uload the rx data
if (uld_rx_data) begin
    rx_data <= rx_reg;
    rx_empty <= 1;
end
// Receive data only when rx is enabled
if (rx_enable) begin
    // Check if just received start of frame
if (!rx_busy && !rx_d2) begin
      rx_busy       <= 1;
      rx_sample_cnt <= 1;
      rx_cnt        <= 0;
    end
    // Start of frame. detected, Proceed with rest of data
    if (rx_busy) begin
       rx_sample_cnt <= rx_sample_cnt + 1;
       // Logic to sample at middle of data
       if (rx_sample_cnt == 7) begin
          if ((rx_d2 == 1) && (rx_cnt == 0)) begin
            rx_busy <= 0;
          end else begin
            rx_cnt <= rx_cnt + 1;
            // Start storing the rx data
            if (rx_cnt > 0 && rx_cnt < 9) begin
              rx_reg[rx_cnt - 1] <= rx_d2;
            end
            if (rx_cnt == 9) begin
               rx_busy <= 0;
               // Check if End of frame. received correctly
               if (rx_d2 == 0) begin
                 rx_frame_err <= 1;
               end else begin

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