使用现有测试设备和平台实现串行RapidIO协议分析

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Design validation of parallel buses is challenging but fairly straight forward.　Parallel busses by nature are made up of an address bus, a data bus (sometimes multiplexed), control signals and a clock.　More sophisticated high speed parallel buses may even contain several clocks, thus creating multiple time domains.　The tools that engineers use to validate these busses are available and are a fairly close match, architecturally, to the task of attaching and decoding parallel busses.　These tools are generally scopes and　logic analyzers.， 大小：7.14 MB