VHDL设计的串口通信程序

文章摘要： rxd_reg1 <= rxd; rxd_reg2 <= rxd_reg1; IF (state_rec = "0000") THEN IF (recstart_tmp = ’1’) THEN recstart <= ’1’; recstart_tmp <= ’0’; state_rec <= state_rec + "0001";

VHDL设计的串口通信程序,标签：eda技术,eda技术实用教程,http://www.88dzw.com
         rxd_reg1 <= rxd;   
         rxd_reg2 <= rxd_reg1;   
         IF (state_rec = "0000") THEN
            IF (recstart_tmp = ’1’) THEN
               recstart <= ’1’;   
               recstart_tmp <= ’0’;   
               state_rec <= state_rec + "0001";   
            ELSE
               IF ((NOT rxd_reg1 AND rxd_reg2) = ’1’) THEN 检测到起始位的下降沿，进入接受状态
                  recstart_tmp <= ’1’;   
               END IF;
            END IF;
         ELSE
            IF (state_rec >= "0001" AND state_rec<="1000") THEN
               IF (clkbaud_rec = ’1’) THEN
                  rxd_buf(7) <= rxd_reg2;   
                  rxd_buf(6 DOWNTO 0) <= rxd_buf(7 DOWNTO 1);   
                  state_rec <= state_rec + "0001";   
               END IF;
            ELSE
               IF (state_rec = "1001") THEN
                  IF (clkbaud_rec = ’1’) THEN
                     state_rec <= "0000";   
                     recstart <= ’0’;   
                  END IF;
               END IF;
            END IF;
         END IF;
      END IF;
 END IF;
   END PROCESS;

   PROCESS(rxd_buf)   将接受的数据用数码管显示出来

上一页  [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]  下一页