VHDL设计的串口通信程序

文章摘要： key_entry2 <= ’0’; state_tras <= "0000"; END IF; END IF; WHEN "0001" => 发送第1位 IF (clkbaud_tras = ’1’) THEN

VHDL设计的串口通信程序,标签：eda技术,eda技术实用教程,http://www.88dzw.com
                              key_entry2 <= ’0’;   
                              state_tras <= "0000";   
                           END IF;
                        END IF;
               WHEN "0001" => 发送第1位
                        IF (clkbaud_tras = ’1’) THEN
                           txd_reg <= txd_buf(0);   
                           txd_buf(6 DOWNTO 0) <= txd_buf(7 DOWNTO 1);   
                           state_tras <= state_tras + "0001";   
                        END IF;
               WHEN "0010" =>  发送第2位
                        IF (clkbaud_tras = ’1’) THEN
                           txd_reg <= txd_buf(0);   
                           txd_buf(6 DOWNTO 0) <= txd_buf(7 DOWNTO 1);   
                           state_tras <= state_tras + "0001";   
                        END IF;
               WHEN "0011" =>  发送第3位
                        IF (clkbaud_tras = ’1’) THEN
                           txd_reg <= txd_buf(0);   

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