用STATECAD快速设计有限状态机
[11-20 16:12:53] 来源:http://www.88dzw.com FPGA 阅读:8911次
文章摘要: WHEN POWERON => IF ( POWERSWITCH='0' ) THEN next_sreg<=OFF; next_POWERLED<='0'; next_PLAYLED<='0'; next_RECORDLED<='0'; ELSIF ( RECORDSWITCH='1' ) THEN next_sreg<=RECORDING; next_POWERLED<='1'; next_PLAYLE
用STATECAD快速设计有限状态机,标签:fpga是什么,fpga教程,http://www.88dzw.comWHEN POWERON =>
IF ( POWERSWITCH='0' ) THEN
next_sreg<=OFF; next_POWERLED<='0';
next_PLAYLED<='0'; next_RECORDLED<='0';
ELSIF ( RECORDSWITCH='1' ) THEN
next_sreg<=RECORDING; next_POWERLED<='1';
next_PLAYLED<='0'; next_RECORDLED<='1';
ELSIF ( PLAYSWITCH='1' ) THEN
next_sreg<=PLAY; next_POWERLED<='1';
next_PLAYLED<='1'; next_RECORDLED<='0';
ELSE
next_sreg<=POWERON; next_POWERLED<='1';
next_PLAYLED<='0'; next_RECORDLED<='0';
END IF;
WHEN RECORDING =>
IF ( POWERSWITCH='1' AND STOPSWITCH='0' ) THEN
next_sreg<=RECORDING; next_POWERLED<='1';
next_PLAYLED<='0'; next_RECORDLED<='1';
END IF;
IF ( POWERSWITCH='0' ) THEN
next_sreg<=OFF; next_POWERLED<='0';
next_PLAYLED<='0'; next_RECORDLED<='0';
END IF;
IF ( STOPSWITCH='1' AND POWERSWITCH='1' ) THEN
next_sreg<=POWERON; next_POWERLED<='1';
next_PLAYLED<='0'; next_RECORDLED<='0';
END IF;
WHEN OTHERS =>
END CASE;
END PROCESS;
END BEHAVIOR;
整个状态机实现过程比相当简单。快捷。有效。
Tag:FPGA,fpga是什么,fpga教程,FPGA
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