ADC0809 VHDL控制程序

[11-20 16:14:44]   来源:http://www.88dzw.com  FPGA   阅读:8394

文章摘要: if eoc='0' then next_state<=st4; --检测EOC的上升沿else next_state<=st5;end if; when st5=>next_state<=st6;ale<='0';start<='0';en<='1'; when st6=>next_state<=st0;ale<='0';start<='0';en<=&

ADC0809 VHDL控制程序,标签:fpga是什么,fpga教程,http://www.88dzw.com
        if eoc='0' then next_state<=st4;                            --检测EOC的上升沿
else next_state<=st5;
end if;
  when st5=>next_state<=st6;ale<='0';start<='0';en<='1';
  when st6=>next_state<=st0;ale<='0';start<='0';en<='1';regl<=d;
  when others=> next_state<=st0;ale<='0';start<='0';en<='0';
  end case;
end process;
clock:process(clk)                 --对系统时钟进行分频,得到ADC0809转换工作时钟
begin
 if clk'event and clk='1' then qq<=qq+1;              --在clk1的上升沿,转换至下一状态
if QQ="01111111" THEN clk1<='1'; current_state <=next_state;   
  elsif qq<="01111111" then clk1<='0'; 
    end if; 
end if;
end process;
q<=regl;  abc_out<=abc_in; 
end behav; 

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