出租车计价器VHDL程序与仿真

文章摘要：signal en1,en0,f:std_logic; --使能信号 beginfeipin:process(clk_240,start)begin if clk_240'event and clk_240='1' then if start='0' then q_15<=0;q_16<=0;f_15<='0';f_16<='0';f_1<='0';f<='0'; else

出租车计价器VHDL程序与仿真,标签：fpga是什么,fpga教程,http://www.88dzw.com
signal en1,en0,f:std_logic;                             --使能信号
begin

feipin:process(clk_240,start)
begin
  if clk_240'event and clk_240='1' then
     if start='0' then q_15<=0;q_16<=0;f_15<='0';f_16<='0';f_1<='0';f<='0';
     else
        if q_15=15 then q_15<=0;f_15<='1';          --此IF语句得到频率为15Hz的信号
        else q_15<=q_15+1;f_15<='0';
        end if;
        if q_16=14 then q_16<=0;f_16<='1';          --此IF语句得到频率为16Hz的信号
        else q_16<=q_16+1;f_16<='0';
        end if;
        if q_1=239 then q_1<=0;f_1<='1';            --此IF语句得到频率为1Hz的信号
        else q_1<=q_1+1;f_1<='0';
        end if;
        if en1='1' then f<=f_15;                    --此IF语句得到计费脉冲f
        elsif en0='1' then f<=f_16;
        else f<='0';
        end if;
     end if;
  end if;
end process;

process(f_1)
begin
  if f_1'event and f_1='1' then
     if start='0' then
w<=0;en1<='0';en0<='0';m1<="000";m0<="0000";k1<="0000";k0<="0000";
     elsif stop='1' then
        if w=59 then w<=0;                             --此IF语句完成等待计时
           if m0="1001" then m0<="0000";                --此IF语句完成分计数
              if m1<="101" then m1<="000";
              else m1<=m1+1;
              end if;
           else m0<=m0+1;
           end if;
           if m1&m0>"0000001"then en1<='1';             --此IF语句得到en1使能信号
           else en1<='0';
           end if;

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