Using Timers in the MAXQ Famil

文章摘要：Using the TimerThe Counter RegistersThe counter has three registers associated with it in sixteen-bit mode and three additional registers when in eight-bit mode. These registers can be read and written in either mode (eight- or sixteen-bit), but the low registers behave differently when in eight-bit

Using Timers in the MAXQ Famil,标签：计算机控制技术,工厂电气控制技术,http://www.88dzw.com

Using the Timer

The Counter Registers
The counter has three registers associated with it in sixteen-bit mode and three additional registers when in eight-bit mode. These registers can be read and written in either mode (eight- or sixteen-bit), but the low registers behave differently when in eight-bit mode. When operating in sixteen-bit mode, T2V, T2R and T2C serve as the sixteen-bit counter, reload and compare registers, respectively. When operating in eight-bit mode, these three registers serve as the low-order eight-bit registers. The high-order registers are represented by the T2H, T2RH and T2CH for the counter, reload and compare registers, respectively. Additionally, these registers take on the role of the primary counter, with the T2V, T2R and T2C registers assuming a secondary role.

This means that any code that uses the timer registers will operate significantly differently when the timer is in eight-bit mode versus sixteen-bit mode. Therefore it is recommended that you use either eight-bit mode or sixteen-bit mode exclusively for a particular timer. If you need to use it in both modes at different times, using separate functions for each mode will cause less confusion for the programmer.

In sixteen-bit mode, the T2V register contains the current count. This register is incremented with the selected clock edge(s) when either the run bit (TR2) or the single shot bit (SS2) are turned on and gating is not active (G2EN=0). If gating is active (G2EN=1) then in addition to either TR2 or SS2 being on, the input on the primary pin must be of opposite polarity to the primary polarity bit (T2POL [0]) for the counter to increment.

The T2R register holds the reload value for the counter. This value is automatically inserted into the counter (T2V) whenever it overflows (has reached FFFFh and is due to increment again).

Control and Configuration Registers

There are three control and configuration registers: T2CFG, T2CNA, and T2CNB. T2CFG contains general configuration information.

The C/T2 bit (counter/timer select) selects whether the timer will function in counter mode or timer mode (capture, compare, and capture with compare output are sub-modes of the timer mode). In timer mode, the CCF [1:0] bits (capture/compare select) determine if the timer is in compare mode (CCF [1:0] = 00) or capture mode (CCF [1:0] = 01, 10, or 11). In counter mode, the CCF bits determine which edges - falling, rising, or both - will be counted. In counter mode, a value of 00 in the CCF bits is not used since the counter would have nothing to count. The mode select bit (T2MD) determines if the timer will operate as one sixteen-bit timer or two separate eight-bit timers. When set, two eight-bit timers are selected. The secondary timer is always a compare/PWM timer.

The system clock or the alternate clock (32 kHz RTC clock in some MAXQ implementations) can be selected as the source clock, and each of these can be prescaled as necessary. The alternate clock select bit (T2CI) defaults to 0, which selects the system clock. Setting this bit selects the alternate clock.

The prescaler bits (T2DIV [2:0]) select the clock divisor, which ranges from 1 to 128. The formula for the prescaler is 2n, where n is the value in T2DIV [2:0].

上一页  [1] [2] [3] [4] [5] [6] [7] [8]  下一页