Using Timers in the MAXQ Famil

文章摘要：The following code sets up the capture. ; set up Int handlermove IV, #IntHandler ; Set interrupt vector. move IC.0, #1 ; Enable global interrupts. move IMR.4, #1 ; Enable interrupts for module 3.; timer 0 is in module 3, timer 1 & 2 are in modu

Using Timers in the MAXQ Famil,标签：计算机控制技术,工厂电气控制技术,http://www.88dzw.com
The following code sets up the capture.

; set up Int handler
	move    IV, #IntHandler         ; Set interrupt vector.
      move    IC.0, #1                ; Enable global interrupts.
      move    IMR.4, #1               ; Enable interrupts for module 3.
	; timer 0 is in module 3, timer 1 & 2 are in module 4

	; repeated capture of high pulse
	move T2CFG1, #074h ;
; 0111,0100 -- use system clock (0), divide by 128 (111),
;	16 bit mode (0), capture on falling edge (10), c/t2=timer (0)

	move T2CNA1, #08Fh ;
; 1000,1111 -- ET2 on, interrupt will be generated (1), primary OE off (0),
;	T2POL0 (gating) at low (0), TR2L off, will be set later (0)
;	TR2 on (1), CPRL2 (reload on capture) is on (1),
;   	SS2 on (1), gating enabled (1)

	move 	T2CNB1, #000h
; 0000,0000 -- ET2L off, low interrupt not used (0), secondary OE off (0),
;	T2POL1 = not used (0), reserved(0)
;	TF2 is generated by the timer (0), TF2L is not used (0),
;   	TCC2 is not used (0), TC2L is not used (0)

The following is part of the interrupt handler code:

IntHandler:
	; looking for Timer2 interrupt...

move c, T2CNB1.1 ; capture/reload flag
jump nc, NoCapture
move T2CNB1.1, #0
; put code for capture event here
move ACC, T2C1 ; capture value now in ACC

NoCapture:
move c, T2CNB1.3 ; overflow flag
jump nc, NoOverflow
	move T2CNB1.3, #0 ;
	; put code to deal with overflow here
	; pulse was too long to measure with current clock speed and divisor
	; can add 65536 to a 32-bit value to keep counting

NoOverflow:
	; put other interrupt code here

reti

Counter Example - Count incoming transitions with interrupt and output waveform
The following example counts incoming pulses on the primary pin and generates an interrupt after every eight pulses. It also controls an output waveform on the secondary pin, which is toggled once every eight input pulses.

	; This code sets up the timer and should be run once
	; set up Int handler
	move    IV, #IntHandler	    ; Set interrupt vector.
      move    IC.0, #1            ; Enable global interrupts.
      move    IMR.3, #1           ; Enable interrupts for module 3.
	; timer 0 is in module 3

	move	T2V0, #0FFF8h ; set to reload value
	move 	T2R0, #0FFF8h ; reload value 0x10000 - 0x0ffff = 8 ticks
	move 	T2C0, #00000h ;

	move 	T2CFG0, #003h ;
; 0000,0011 -- use system clock (0), divide by 1 (000),
;	16-bit mode (0), rising edge (01), c/t2=counter (1)

	move 	T2CNB0, #060h
; 0110,0000 -- ET2L not used (0), secondary OE on (1),
;	T2POL1 start at high (1), reserved(0)
;	TF2 is generated by the timer (0), TF2L is not used (0),
;   	TCC2 is generated by the timer (0), TC2L is not used (0)

	move 	T2CNA0, #088h
; 1000,1000 -- ET2 on, interrupt will be generated (1), primary OE not used (0),
;	T2POL0 is not used (0), TR2L is not needed(0)
;	TR2 on (1), CPRL2 is not needed (0),
;   	SS2 is not needed (0), gating disabled (0)

The following is part of the interrupt handler

IntHandler:

	move c, T2CNB0.3
	jump nc, NoTimer
	move T2CNB0.3, #0 ; service interrupt
	; put code for every 8 pulses here

NoTimer:
	; other interrupt code here

reti

Some Common Pitfalls to Avoid

When in compare mode, if the compare and reload values are equal a second transition on the output occurs one clock cycle after a reload occurs. While this is a valid option when you want a pulse width of just one clock cycle, it's easy to let this happen without intending it since they both default to the same value of 0. If the compare value is not to be used it should be set outside of the range used by the timer. Normally setting the compare value to something less than the reload value will do this. If this is not possible (due to using a reload value of 0) then the compare value should be set to FFFFh in sixteen-bit mode or FFh in eight-bit mode. This causes the compare and overflow events to happen on the same timer clock cycle preventing the second transition of the output.

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