Using Timers in the MAXQ Famil

文章摘要：Abstract: This application note describes how to set up and use the Type 2 Timers in the MAXQ™ Family of Microcontrollers for different applications. It includes source code for reference. IntroductionThe MAXQ family of microcontrollers has three types of timers: Timer 0, Timer 1, and Timer 2.

Using Timers in the MAXQ Famil,标签：计算机控制技术,工厂电气控制技术,http://www.88dzw.com
Abstract: This application note describes how to set up and use the Type 2 Timers in the MAXQ™ Family of Microcontrollers for different applications. It includes source code for reference.

Introduction

The MAXQ family of microcontrollers has three types of timers: Timer 0, Timer 1, and Timer 2.

The MAXQ Timer 0 type is modeled after the Timer 0 type common on many 8051 microcontollers. The MAXQ Timer 1 type is modeled after the 8051 Timer 2 type. Most MAXQ products have a new timer called Timer 2 that is unique to the MAXQ family. This application note details how to set up and use this new Timer 2 for different purposes, and includes some source code for reference.

Overview

Functionality
The three main uses of the timer are to generate output waveforms, to count transitions of an input signal (including counting system clock transitions thus functioning as a timer), and to time an input signal. This section covers methods to use the configuration modes of Timer 2 to perform these timer functions.

Compare
In this mode, the counter is sourced internally by either the system clock or an alternate clock (typically the 32,768 Hz RTC clock), either of which may be optionally prescaled by 1, 2, 4, 8, 16, 32, 64, or 128. The counter is then used to control the output of the primary and/or secondary timer pins to generate various waveforms.

By changing the values in the reload (T2R) and compare (T2C) registers, the frequency and duty cycle of the output waveforms can be modified. In this way, the MAXQ processor can generate a pulse-width modulated (PWM) waveform. The outputs can be selectively enabled and the starting polarity can be inverted. The limits on frequency and duty cycle are determined by the frequency of the clock selected as source (whether the system or alternate clock) and the clock divisor selected. The minimum pulse width is one clock cycle (selected by setting the compare and reload values to the same value or by setting the compare value to FFFEh) of the prescaled source clock. The maximum pulse width is 65,536 cycles of the prescaled source clock. With a prescale factor of 128, the maximum pulse width is 8,388,608 system clock periods - over eight seconds for a 1 MHz system clock. Using the alternate clock with a lower frequency can increase this even further.

Compare mode also provides the ability to generate single pulses by use of the single shot (SS2) capability. Single shot allows the firmware to set up the length of the pulse before it is triggered, precluding the requirement for firmware to time the pulse and determine when it should end. Gating allows the primary pin to trigger a single pulse on the secondary output or to turn the counter on and off, allowing a PWM output on the secondary pin to be modified by an incoming signal. The compare mode can also be used to generate recurring interrupts on a specific schedule.

Capture
In this mode, the counter is sourced internally but is used to count or time the duration of an input signal on the primary timer pin. The counter can be gated and triggered on either or both edges of the input signal, allowing flexibility in timing pulses, single events, or reccurring waveforms. The value in the T2C register can be used to calculate the period of the measured event.

Counter
In this mode, the primary timer pin sources the clock for the counter. In this mode, the counter counts the transitions on the primary pin, either the rising or falling edges, or both. The secondary pin can be used to output a waveform, which toggles when the count overflows and when the counter matches a specific value. Interrupts can also be generated in these two cases.

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